SiP Layout and Analysis Design Tool/Flow

This presentation will outline a novel design methodology that overcomes many of today’s challenges for co-designing and co-analyzing multi-chip(let) packages.

Speaker John Park of Cadence Design Systems
John Park brings over 35 years of design and EDA experience to his role as Product Management Director for Advanced Semiconductor Packaging at Cadence Design Systems. In this role, John leads a team responsible for defining cross-domain solutions and methodologies for IC, package & PCB co-design and analysis.

This webinar will be hosted via MS Teams. Registrants will receive an email prior to the start of the webinar with login instructions. Please register here for the event. Registration is free for IMAPS members, including student members. The participation fee for non-members is $50.